Ticket #9323: 0002-Fix-fillrect-acceleration.patch

File 0002-Fix-fillrect-acceleration.patch, 7.5 kB (added by jon.nettleton, 4 years ago)

Fix some previous Errors

  • drivers/video/via/accel.c

    From 8e33085348b6845b14b047be716b162448275a84 Mon Sep 17 00:00:00 2001
    From: Jon Nettleton <jon.nettleton@gmail.com>
    Date: Thu, 3 Jun 2010 09:48:14 -0700
    Subject: [PATCH] Fix fillrect acceleration
    
    With the M1 Engine Reg changes the Solid Fill blit no longer uses
    the FGCOLOR register.  Because the old engine doesn't have this
    register we end up with a duplicate key and can no longer use
    an array just for the new registers.  I have duplicated the system
    that we use in the openchrome driver.
    ---
     drivers/video/via/accel.c    |   54 +++++++++++++++++++++++++----------------
     drivers/video/via/accel.h    |   20 ++++++++++++++-
     drivers/video/via/viafbdev.c |   28 +++++++++++-----------
     3 files changed, 65 insertions(+), 37 deletions(-)
    
    diff --git a/drivers/video/via/accel.c b/drivers/video/via/accel.c
    index e48929d..51a038c 100644
    a b  
    2020 */ 
    2121#include "global.h" 
    2222 
     23static u_int8_t via_eng_reg[] = { 
     24        [REG_GECMD]             = VIA_REG_GECMD, 
     25        [REG_GEMODE]    = VIA_REG_GEMODE, 
     26        [REG_SRCPOS]    = VIA_REG_SRCPOS, 
     27        [REG_DSTPOS]    = VIA_REG_DSTPOS, 
     28        [REG_DIMENSION] = VIA_REG_DIMENSION, 
     29        [REG_FGCOLOR]   = VIA_REG_FGCOLOR, 
     30        [REG_BGCOLOR]   = VIA_REG_BGCOLOR, 
     31        [REG_SRCBASE]   = VIA_REG_SRCBASE, 
     32        [REG_DSTBASE]   = VIA_REG_DSTBASE, 
     33        [REG_PITCH]             = VIA_REG_PITCH, 
     34        [REG_MONOPATFGC]        = VIA_REG_FGCOLOR, 
     35        [REG_MONOPATBGC]        = VIA_REG_BGCOLOR, 
     36}; 
     37 
    2338/* Somehow, the M1 engine has the registers in slightly different 
    2439 * locations than previous 2D acceleration engines */ 
    2540static u_int8_t via_m1_eng_reg[] = { 
    26         [VIA_REG_GECMD]         = VIA_REG_GECMD_M1, 
    27         [VIA_REG_GEMODE]        = VIA_REG_GEMODE_M1, 
    28         [VIA_REG_SRCPOS]        = VIA_REG_SRCPOS_M1, 
    29         [VIA_REG_DSTPOS]        = VIA_REG_DSTPOS_M1, 
    30         [VIA_REG_DIMENSION]     = VIA_REG_DIMENSION_M1, 
    31         [VIA_REG_PATADDR]       = VIA_REG_PATADDR_M1, 
    32         [VIA_REG_FGCOLOR]       = VIA_REG_FGCOLOR_M1, 
    33         [VIA_REG_BGCOLOR]       = VIA_REG_BGCOLOR_M1, 
    34         [VIA_REG_CLIPTL]        = VIA_REG_CLIPTL_M1, 
    35         [VIA_REG_CLIPBR]        = VIA_REG_CLIPBR_M1, 
    36         [VIA_REG_OFFSET]        = VIA_REG_OFFSET_M1, 
    37         [VIA_REG_KEYCONTROL]    = VIA_REG_KEYCONTROL_M1, 
    38         [VIA_REG_SRCBASE]       = VIA_REG_SRCBASE_M1, 
    39         [VIA_REG_DSTBASE]       = VIA_REG_DSTBASE_M1, 
    40         [VIA_REG_PITCH]         = VIA_REG_PITCH_M1, 
    41         [VIA_REG_MONOPAT0]      = VIA_REG_MONOPAT0_M1, 
    42         [VIA_REG_MONOPAT1]      = VIA_REG_MONOPAT1_M1, 
     41        [REG_GECMD]             = VIA_REG_GECMD_M1, 
     42        [REG_GEMODE]    = VIA_REG_GEMODE_M1, 
     43        [REG_SRCPOS]    = VIA_REG_SRCPOS_M1, 
     44        [REG_DSTPOS]    = VIA_REG_DSTPOS_M1, 
     45        [REG_DIMENSION] = VIA_REG_DIMENSION_M1, 
     46        [REG_FGCOLOR]   = VIA_REG_FGCOLOR_M1, 
     47        [REG_BGCOLOR]   = VIA_REG_BGCOLOR_M1, 
     48        [REG_SRCBASE]   = VIA_REG_SRCBASE_M1, 
     49        [REG_DSTBASE]   = VIA_REG_DSTBASE_M1, 
     50        [REG_PITCH]             = VIA_REG_PITCH_M1, 
     51        [REG_MONOPATFGC]        = VIA_REG_MONOPATFGC_M1, 
     52        [REG_MONOPATBGC]        = VIA_REG_MONOPATBGC_M1, 
    4353}; 
    4454 
    4555#if defined(CONFIG_FB_VIA_CAMERA) || defined(CONFIG_FB_VIA_CAMERA_MODULE) 
     
    6474        if (viaparinfo->chip_info->twod_engine == VIA_2D_ENG_M1 && 
    6575            reg < ARRAY_SIZE(via_m1_eng_reg)) 
    6676                reg = via_m1_eng_reg[reg]; 
     77        else if (reg < ARRAY_SIZE(via_eng_reg)) 
     78                reg = via_eng_reg[reg]; 
    6779 
    6880        writel(val, viaparinfo->io_virt + reg); 
    6981} 
     
    272284                dwGEMode |= VIA_GEM_8bpp; 
    273285                break; 
    274286        } 
    275         viafb_2d_writel(dwGEMode, VIA_REG_GEMODE); 
     287        viafb_2d_writel(dwGEMode, REG_GEMODE); 
    276288 
    277289        /* Set source and destination base */ 
    278290        base = ((void *)info->screen_base - viafb_FB_MM); 
    279         viafb_2d_writel(base >> 3, VIA_REG_SRCBASE); 
    280         viafb_2d_writel(base >> 3, VIA_REG_DSTBASE); 
     291        viafb_2d_writel(base >> 3, REG_SRCBASE); 
     292        viafb_2d_writel(base >> 3, REG_DSTBASE); 
    281293 
    282294        /* Set source and destination pitch (128bit aligned) */ 
    283295        pitch = (viaparinfo->hres * viaparinfo->bpp >> 3) >> 3; 
    284296        pitch_reg = pitch | (pitch << 16); 
    285297        if (viaparinfo->chip_info->twod_engine != VIA_2D_ENG_M1) 
    286298                pitch_reg |= VIA_PITCH_ENABLE; 
    287         viafb_2d_writel(pitch_reg, VIA_REG_PITCH); 
     299        viafb_2d_writel(pitch_reg, REG_PITCH); 
    288300} 
    289301 
    290302void viafb_hw_cursor_init(void) 
  • drivers/video/via/accel.h

    diff --git a/drivers/video/via/accel.h b/drivers/video/via/accel.h
    index 9a39ed1..10dc704 100644
    a b  
    9191#define VIA_REG_DSTCOLORKEY_M1  0x04C       /* as same as VIA_REG_FG */ 
    9292#define VIA_REG_BGCOLOR_M1      0x050 
    9393#define VIA_REG_SRCCOLORKEY_M1  0x050       /* as same as VIA_REG_BG */ 
    94 #define VIA_REG_MONOPATFGC_M1   0x058       /* Add BG color of Pattern. */ 
    95 #define VIA_REG_MONOPATBGC_M1   0x05C       /* Add FG color of Pattern. */ 
     94#define VIA_REG_MONOPATFGC_M1   0x058       /* Add FG color of Pattern. */ 
     95#define VIA_REG_MONOPATBGC_M1   0x05C       /* Add BG color of Pattern. */ 
    9696#define VIA_REG_COLORPAT_M1     0x100       /* from 0x100 to 0x1ff */ 
    9797 
    9898/* VIA_REG_PITCH(0x38): Pitch Setting */ 
     
    199199 
    200200#define MAXLOOP                 0xFFFFFF 
    201201 
     202 
     203enum via_reg_lookup { 
     204    REG_GECMD, 
     205    REG_GEMODE, 
     206    REG_SRCPOS, 
     207    REG_DSTPOS, 
     208    REG_DIMENSION, 
     209    REG_FGCOLOR, 
     210    REG_BGCOLOR, 
     211    REG_SRCBASE, 
     212    REG_DSTBASE, 
     213    REG_PITCH, 
     214    REG_MONOPATFGC, 
     215    REG_MONOPATBGC 
     216}; 
     217 
    202218void viafb_2d_writel(u_int32_t val, u_int32_t reg); 
    203219void viafb_init_accel(void); 
    204220void viafb_init_2d_engine(void); 
  • drivers/video/via/viafbdev.c

    diff --git a/drivers/video/via/viafbdev.c b/drivers/video/via/viafbdev.c
    index 0efc6e1..3361b08 100644
    a b  
    896896        viafb_set_2d_mode(info); 
    897897 
    898898        /* BitBlt Destination Address */ 
    899         viafb_2d_writel(((rect->dy << 16) | rect->dx), VIA_REG_DSTPOS); 
     899        viafb_2d_writel(((rect->dy << 16) | rect->dx), REG_DSTPOS); 
    900900        /* Dimension: width & height */ 
    901901        viafb_2d_writel((((rect->height - 1) << 16) | (rect->width - 1)), 
    902                         VIA_REG_DIMENSION); 
     902                        REG_DIMENSION); 
    903903        /* Forground color or Destination color */ 
    904         viafb_2d_writel(col, VIA_REG_FGCOLOR); 
     904        viafb_2d_writel(col, REG_MONOPATFGC); 
    905905        /* GE Command */ 
    906         viafb_2d_writel((0x01 | 0x2000 | (rop << 24)), VIA_REG_GECMD); 
     906        viafb_2d_writel((0x01 | 0x2000 | (rop << 24)), REG_GECMD); 
    907907 
    908908} 
    909909 
     
    938938        viafb_set_2d_mode(info); 
    939939 
    940940        /* BitBlt Source Address */ 
    941         viafb_2d_writel(((sy << 16) | sx), VIA_REG_SRCPOS); 
     941        viafb_2d_writel(((sy << 16) | sx), REG_SRCPOS); 
    942942        /* BitBlt Destination Address */ 
    943         viafb_2d_writel(((dy << 16) | dx), VIA_REG_DSTPOS); 
     943        viafb_2d_writel(((dy << 16) | dx), REG_DSTPOS); 
    944944        /* Dimension: width & height */ 
    945945        viafb_2d_writel((((area->height - 1) << 16) | (area->width - 1)), 
    946                         VIA_REG_DIMENSION); 
     946                        REG_DIMENSION); 
    947947        /* GE Command */ 
    948         viafb_2d_writel((0x01 | direction | (0xCC << 24)), VIA_REG_GECMD); 
     948        viafb_2d_writel((0x01 | direction | (0xCC << 24)), REG_GECMD); 
    949949 
    950950} 
    951951 
     
    981981        viafb_set_2d_mode(info); 
    982982 
    983983        /* BitBlt Source Address */ 
    984         viafb_2d_writel(0x0, VIA_REG_SRCPOS); 
     984        viafb_2d_writel(0x0, REG_SRCPOS); 
    985985        /* BitBlt Destination Address */ 
    986         viafb_2d_writel(((image->dy << 16) | image->dx), VIA_REG_DSTPOS); 
     986        viafb_2d_writel(((image->dy << 16) | image->dx), REG_DSTPOS); 
    987987        /* Dimension: width & height */ 
    988988        viafb_2d_writel((((image->height - 1) << 16) | (image->width - 1)), 
    989                         VIA_REG_DIMENSION); 
     989                        REG_DIMENSION); 
    990990        /* fb color */ 
    991         viafb_2d_writel(fg_col, VIA_REG_FGCOLOR); 
     991        viafb_2d_writel(fg_col, REG_FGCOLOR); 
    992992        /* bg color */ 
    993         viafb_2d_writel(bg_col, VIA_REG_BGCOLOR); 
     993        viafb_2d_writel(bg_col, REG_BGCOLOR); 
    994994        /* GE Command */ 
    995         viafb_2d_writel(0xCC020142, VIA_REG_GECMD); 
     995        viafb_2d_writel(0xCC020142, REG_GECMD); 
    996996 
    997997        for (i = 0; i < size / 4; i++) { 
    998998                writel(*udata, viaparinfo->io_virt + VIA_MMIO_BLTBASE);