Ticket #9350: left-br.reg

File left-br.reg, 17.6 kB (added by martin.langhoff, 3 years ago)

Left orientation - broken after resume

Line 
1via-chrome-tool (C) 2009 by VIA Technologies, Inc.
2This is FREE SOFTWARE with ABSOLUTELY NO WARRANTY
3
4Sequencer register dump:
5    0x00 = 0x00 (Reset)
6    0x01 = 0x01 (Clocking Mode)
7    0x02 = 0x0f (Map Mask)
8    0x03 = 0x00 (Character Map Select)
9    0x04 = 0x06 (Memory Mode)
10    0x10 = 0x01 (Extended Register Unlock)
11    0x11 = 0x78 (Configuration 0)
12    0x12 = 0x00 (Configuration 1)
13    0x13 = 0x00 (Configuration 2 (DVP1 strapping))
14    0x14 = 0x00 (Frame Buffer Size Control)
15    0x15 = 0x00 (Display Mode Control)
16    0x16 = 0x60 (Display FIFO Threshold Control)
17    0x17 = 0x1f (Display FIFO Control)
18    0x18 = 0x4e (Display Arbiter Control 0)
19    0x19 = 0x7f (Power Management)
20       0x01 CPU Interface Clock Control: 0x01
21       0x02 Display Interface Clock Control: 0x02
22       0x04 MC Interface Clock Control: 0x04
23       0x08 Typical Arbiter Interface Clock Control: 0x08
24       0x10 AGP Interface Clock Control: 0x10
25       0x20 P-Arbiter Interface Clock Control: 0x20
26       0x40 MIU/AGP Interface Clock Control: 0x40
27    0x1a = 0x30 (PCI Bus Control)
28    0x1b = 0xf0 (Power Management Control 0)
29       0x01 Primary Display's LUT Off: 0x00
30       0x18 Primary Display Engine VCK Gating: 0x10
31       0x60 Secondary Display Engine LCK Gating: 0x60
32    0x1c = 0x00 (Horizontal Display Fetch Count Data)
33    0x1d = 0x00 (Horizontal Display Fetch Count Control)
34    0x1e = 0xf1 (Power Management Control)
35       0x01 ROC ECK: 0x01
36       0x02 Replace ECK by MCK: 0x00
37       0x08 Spread Spectrum: 0x00
38       0x30 DVP1 Power Control: 0x30
39       0xc0 VCP Power Control: 0xc0
40    0x20 = 0x00 (Typical Arbiter Control 0)
41    0x21 = 0x18 (Typical Arbiter Control 1)
42    0x22 = 0x14 (Display Arbiter Control 1)
43    0x26 = 0x3d (IIC Serial Port Control 0)
44    0x2a = 0x0c (Power Management Control 5)
45       0x03 LVDS Channel 1 Pad Control: 0x00
46       0x0c LVDS Channel 2 Pad Control: 0x0c
47       0x40 Sprad Spectrum Type FIFO: 0x00
48    0x2b = 0x00 (LVDS Interrupt Control)
49       0x01 MSI Pending IRQ Re-trigger: 0x00
50       0x02 CRT Hot Plug Detect Enable: 0x00
51       0x04 CRT Sense IRQ status: 0x00
52       0x08 CRT Sense IRQ enable: 0x00
53       0x10 LVDS Sense IRQ status: 0x00
54       0x20 LVDS Sense IRQ enable: 0x00
55    0x2c = 0xc2 (General Purpose I/O Port)
56    0x2d = 0xff (Power Management Control 1)
57       0x03 ECK Pll Power Control: 0x03
58       0x0c LCK PLL Power Control: 0x0c
59       0x30 VCK PLL Powre Control: 0x30
60       0xc0 E3_ECK_N Selection: 0xc0
61    0x2e = 0xff (Power Management Control 2)
62       0x03 Video Playback Engine V3/V4 Gated Clock VCK: 0x03
63       0x0c PCI Master / DMA Gated Clock ECK/CPUCK: 0x0c
64       0x30 Video Processor Gated Clock ECK: 0x30
65       0xc0 Capturer Gated Clock ECK: 0xc0
66    0x31 = 0x00 (IIC Serial Port Control 1)
67    0x35 = 0x2d (Subsystem Vendor ID Low)
68    0x36 = 0x15 (Subsystem Vendor ID High)
69    0x37 = 0x33 (Subsystem ID Low)
70    0x38 = 0x08 (Subsystem ID High)
71    0x39 = 0x10 (BIOS Reserved Register 0)
72    0x3a = 0x00 (BIOS Reserved Register 1)
73    0x3b = 0x01 (PCI Revision ID Back Door)
74    0x3c = 0x1d (Miscellaneous)
75       0x01 AGP Bus Pack Door AGP3 Enable: 0x01
76       0x02 Switch 3 PLLs to Prime Output: 0x00
77       0x04 LCDCK PLL Locked Detect: 0x04
78       0x08 VCK PLL Locked Detect: 0x08
79       0x10 ECL PLL Locked Detect: 0x10
80       0x60 PLL Frequency Division Select for Testing: 0x00
81    0x3d = 0x06 (General Purpose I/O Port)
82    0x3e = 0x20 (Miscellaneous Register for AGP Mux)
83    0x3f = 0xff (Power Management Control 2)
84       0x03 Video Clock Control (Gated ECK): 0x03
85       0x0c 2D Clock Control (Gated ECK/CPUCK): 0x0c
86       0x30 3D Clock Control (Gated ECK): 0x30
87       0xc0 CR Clock Control (Gated ECK): 0xc0
88    0x40 = 0x00 (PLL Control)
89       0x01 Reset ECK PLL: 0x00
90       0x02 Reset VCK PLL: 0x00
91       0x04 Reset LCDCK PLL: 0x00
92       0x08 LVDS Interrupt Method: 0x00
93       0x30 Free Run ECK Frequency within Idle Mode: 0x00
94       0x80 CRT Sense Enable: 0x00
95    0x41 = 0xb0 (Typical Arbiter Control 1)
96    0x42 = 0x10 (Typical Arbiter Control 1)
97    0x43 = 0xff (Graphics Bonding Option)
98       0x01 Notebook Used Flag: 0x01
99       0x04 Typical Channel 1 Arbiter Read Back Data Overwrite Flag: 0x04
100       0x08 Typical Channel 0 Arbiter Read Back Data Overwrite Flag: 0x08
101       0x10 IGA1 Display FIFO Underflow Flag: 0x10
102       0x20 IGA2 Dispaly FIFO Underflow Flag: 0x20
103       0x40 Windows Media Video Enable Flag: 0x40
104       0x80 Advance Video Enable Flag: 0x80
105    0x44 = 0x54 (VCK Clock Synthesizer Vallue 0)
106    0x45 = 0x90 (VCK Clock Synthesizer Vallue 1)
107    0x46 = 0x03 (VCK Clock Synthesizer Vallue 2)
108    0x47 = 0x79 (ECK Clock Synthesizer Vallue 0)
109    0x48 = 0x88 (ECK Clock Synthesizer Vallue 1)
110    0x49 = 0x04 (ECK Clock Synthesizer Vallue 2)
111    0x4a = 0x9f (LDCK Clock Synthesizer Value 0)
112    0x4b = 0x0c (LDCK Clock Synthesizer Value 1)
113    0x4c = 0x05 (LDCK Clock Synthesizer Value 2)
114    0x4d = 0x30 (Preemptive Arbiter Control)
115    0x4e = 0x00 (Software Reset Control)
116    0x4f = 0x5f (CR Gating Clock Control)
117    0x50 = 0x1f (AGP Control)
118    0x51 = 0x81 (Display FIFO Control 1)
119    0x52 = 0x00 (Integrated TV Shadow Register Control)
120    0x53 = 0xff (DAC Sense Control 1)
121    0x54 = 0x00 (DAC Sense Control 2)
122    0x55 = 0x00 (DAC Sense Control 3)
123    0x56 = 0xff (DAC Sense Control 4)
124    0x57 = 0x00 (Display FIFO Control 2)
125    0x58 = 0x08 (GFX Power Control 1)
126    0x59 = 0xdf (GFX Power Control 2)
127       0x01 GFX-NM AGP Dynamic Clock Enable: 0x01
128       0x02 GFX-NM GMINT Channel 0 Dynamic Clock Enable: 0x02
129       0x04 GFX-NM GMINT Channel 1 Dynamic Clock Enable: 0x04
130       0x08 GFX-NM PCIC Dynamic Clock Enable: 0x08
131       0x10 GFX-NM IGA Dynamic Clock Enable: 0x10
132       0x20 IGA Low Thrshold Enable: 0x00
133       0x80 IGA1 Enable: 0x80
134    0x5a = 0x00 (PCI Bus Control 2)
135    0x5b = 0x51 (Device Used Status 0)
136       0x01 LVDS1 Used IGA2 Source: 0x01
137       0x02 LBDS1 Used IGA1 Source: 0x00
138       0x04 LVDS0 Used IGA2 Source: 0x00
139       0x08 LVDS1 Used IGA1 Source: 0x00
140       0x10 DAC0 Used IGA2 Source: 0x10
141       0x20 DAC0 Used IGA1 Source: 0x00
142       0x40 DAC0 User is TV: 0x40
143       0x80 DCVI Source Selection is TV: 0x00
144    0x5c = 0x29 (Device Used Status 1)
145       0x01 DVP1 Used IGA2 Source: 0x01
146       0x02 DVP1 Used IGA1 Source: 0x00
147       0x10 DAC1 Used IGA2 Source: 0x00
148       0x20 DAC1 Used IGA1 Source: 0x20
149       0x40 DAC1 User is TV: 0x00
150    0x5d = 0x00 (Timer Control)
151    0x5e = 0x00 (DAC Control 2)
152    0x60 = 0x00 (I2C Mode Control)
153    0x61 = 0x00 (I2C Host Address)
154    0x62 = 0x00 (I2C Host Data)
155    0x63 = 0x00 (I2C Host Control)
156    0x64 = 0x20 (I2C Status)
157    0x65 = 0x00 (Power Management Control 6)
158    0x66 = 0x20 (GTI Control 0)
159    0x67 = 0x20 (GTI Control 1)
160    0x68 = 0xe0 (GTI Control 1)
161    0x69 = 0x20 (GTI Control 1)
162    0x6a = 0x00 (GTI Control 1)
163    0x6b = 0x00 (GTI Control 1)
164    0x6c = 0x00 (GTI Control 1)
165    0x6d = 0xe0 (GTI Control 1)
166    0x6e = 0x01 (GTI Control 1)
167    0x6f = 0x00 (GTI Control 1)
168    0x70 = 0x20 (GARB Control 0)
169    0x71 = 0x04 (Typical Arbiter Control 2)
170    0x72 = 0x0f (Typical Arbiter Control 3)
171    0x73 = 0x33 (Typical Arbiter Control 4)
172    0x74 = 0x1f (Typical Arbiter Control 5)
173    0x75 = 0x1f (Typical Arbiter Control 6)
174    0x76 = 0x00 (Backlight Control 1)
175       0x01 Backlight Control Enable: 0x00
176    0x77 = 0x00 (Backlight Control 2)
177    0x78 = 0x60 (Backlight Control 3)
178
179Graphic Controller register dump:
180    0x00 = 0x00 (Set / Reset)
181    0x01 = 0x00 (Enable Set / Reset)
182    0x02 = 0x00 (Color Compare)
183    0x03 = 0x00 (Data Rotate)
184    0x04 = 0x00 (Read Map Select)
185    0x05 = 0x00 (Mode)
186    0x06 = 0x00 (Miscellaneous)
187    0x07 = 0x00 (Color Don't Care)
188    0x08 = 0x00 (Bit Mask)
189    0x20 = 0x00 (Offset Register Control)
190    0x21 = 0x00 (Offset Register A)
191    0x22 = 0x00 (Offset Register B)
192
193CRT controller register dump:
194    0x00 = 0x99 (Horizontal Total)
195    0x01 = 0x95 (Horizontal Display End)
196    0x02 = 0x95 (Start Horizontal Blank)
197    0x03 = 0x9d (End Horizontal Blank)
198    0x04 = 0x97 (Start Horizontal Retrace)
199    0x05 = 0x1b (End Horizontal Retrace)
200    0x06 = 0x8e (Vertical Total)
201    0x07 = 0x00 (Overflow)
202    0x08 = 0x00 (Preset Row Scan)
203    0x09 = 0x00 (Max Scan Line)
204    0x0a = 0x00 (Cursor Start)
205    0x0b = 0x00 (Cursor End)
206    0x0c = 0x00 (Start Address High)
207    0x0d = 0x00 (Start Address Low)
208    0x0e = 0x00 (Cursor Location High)
209    0x0f = 0x00 (Cursor Location Low)
210    0x10 = 0x00 (Vertical Retrace Start)
211    0x11 = 0x00 (Vertical Retrace End)
212    0x12 = 0x00 (Vertical Display End)
213    0x13 = 0x00 (Offset)
214    0x14 = 0x00 (Underline Location)
215    0x15 = 0x00 (Start Vertical Blank)
216    0x16 = 0x00 (End Vertical Blank)
217    0x17 = 0xa3 (CRTC Mode Control)
218    0x18 = 0x00 (Line Compare)
219    0x30 = 0x08 (Display Fetch Blocking Control)
220    0x31 = 0x00 (Half Line Position)
221    0x32 = 0x11 (Mode Control)
222    0x33 = 0x00 (Hsync Adjuster)
223    0x34 = 0x00 (Starting Address Overflow)
224    0x35 = 0x00 (Extended Overflow)
225    0x36 = 0x01 (Power Management Control 3)
226    0x37 = 0x34 (DAC Control)
227    0x38 = 0xdc (Signature Data B0)
228    0x39 = 0x4a (Signature Data B1)
229    0x3a = 0x0d (Signature Data B2)
230    0x3b = 0x01 (Scratch Pad 2)
231    0x3c = 0x08 (Scratch Pad 3)
232    0x3d = 0x64 (Scratch Pad 4)
233    0x3e = 0x20 (Scratch Pad 5)
234    0x3f = 0x0b (Scratch Pad 6)
235    0x40 = 0x00 (Test Mode Control 0)
236    0x43 = 0x80 (IGA1 Display Control)
237    0x45 = 0x00 (Power Now Indicator Control 3)
238    0x46 = 0x00 (Test Mode Control 1)
239    0x47 = 0x00 (Test Mode Control 2)
240    0x48 = 0x00 (Starting Address Overflow)
241    0x50 = 0xd7 (Second CRTC Horizontal Total Period)
242    0x51 = 0xaf (Second CRTC Horizontal Active Data Period)
243    0x52 = 0xaf (Second CRTC Horizontal Blanking Start)
244    0x53 = 0xd7 (Second CRTC Horizontal Blanking End)
245    0x54 = 0x24 (Second CRTC Horizontal Blanking Overflow)
246    0x55 = 0x44 (Second CRTC Horizontal Period Overflow)
247    0x56 = 0xb6 (Second CRTC Horizontal Retrace Start)
248    0x57 = 0xbe (Second CRTC Horizontal Retrace End)
249    0x58 = 0x8f (Second CRTC Vertical Total Period)
250    0x59 = 0x83 (Second CRTC Vertical Active Data Period)
251    0x5a = 0x83 (Second CRTC Vertical Blanking Start)
252    0x5b = 0x8f (Second CRTC Vertical Blanking End)
253    0x5c = 0x9b (Second CRTC Vertical Blanking Overflow)
254    0x5d = 0x1b (Second CRTC Vertical Period Overflow)
255    0x5e = 0x88 (Second CRTC Vertical Retrace Start)
256    0x5f = 0x6e (Second CRTC Vertical Retrace End)
257    0x60 = 0x46 (Second CRTC Vertical Status 1)
258    0x61 = 0x52 (Second CRTC Vertical Status 2)
259    0x62 = 0x00 (Second Display Starting Address Low)
260    0x63 = 0x00 (Second Display Starting Address Middle)
261    0x64 = 0x00 (Second Display Starting Address High)
262    0x65 = 0x2c (Second Display Horizontal Quadword Count)
263    0x66 = 0x58 (Second Display Horizontal Offset)
264    0x67 = 0xd6 (Second Display Col Depth and Horiz Overfl)
265    0x68 = 0xf0 (Second Display Queue Depth and Read Thresh)
266    0x69 = 0x00 (Second Display Interrupt Enable and Status)
267    0x6a = 0xc8 (Second Display Channel and LCD Enable)
268    0x6b = 0x00 (Channel 1 and 2 Clock Mode Selection)
269    0x6c = 0x00 (TV Clock Control)
270    0x6d = 0xff (Horizontal Total Shadow)
271    0x6e = 0x77 (End Horizontal Blanking Shadow)
272    0x6f = 0xef (Vertical Total Shadow)
273    0x70 = 0x7f (Vertical Display Enable End Shadow)
274    0x71 = 0x7f (Vertical Display Overflow Shadow)
275    0x72 = 0x2f (Start Vertical Blank Shadow)
276    0x73 = 0xef (End Vertical Blank Shadow)
277    0x74 = 0xe7 (Vertical Blank Overflow Shadow)
278    0x75 = 0xee (Vertical Retrace Start Shadow)
279    0x76 = 0x77 (Vertical Retrace End Shadow)
280    0x77 = 0x00 (LCD Horizontal Scaling Factor)
281    0x78 = 0x6f (LCD Vertical Scaling Facor)
282    0x79 = 0x68 (LCD Scaling Control)
283    0x7a = 0x01 (LCD Scaling Parameter 1)
284    0x7b = 0x02 (LCD Scaling Parameter 2)
285    0x7c = 0x03 (LCD Scaling Parameter 3)
286    0x7d = 0x04 (LCD Scaling Parameter 4)
287    0x7e = 0x07 (LCD Scaling Parameter 5)
288    0x7f = 0x0a (LCD Scaling Parameter 6)
289    0x80 = 0x0d (LCD Scaling Parameter 7)
290    0x81 = 0x13 (LCD Scaling Parameter 8)
291    0x82 = 0x16 (LCD Scaling Parameter 9)
292    0x83 = 0x19 (LCD Scaling Parameter 10)
293    0x84 = 0x1c (LCD Scaling Parameter 11)
294    0x85 = 0x1d (LCD Scaling Parameter 12)
295    0x86 = 0x1e (LCD Scaling Parameter 13)
296    0x87 = 0x1f (LCD Scaling Parameter 14)
297    0x88 = 0x60 (LCD Panel Type)
298    0x8a = 0x01 (LCD Timing Control 1)
299    0x8b = 0xca (LCD Power Sequence Control 0)
300    0x8c = 0xca (LCD Power Sequence Control 1)
301    0x8d = 0xca (LCD Power Sequence Control 2)
302    0x8e = 0xca (LCD Power Sequence Control 3)
303    0x8f = 0x11 (LCD Power Sequence Control 4)
304    0x90 = 0x11 (LCD Power Sequence Control 5)
305    0x91 = 0x00 (Software Cotnrol Power Sequence)
306    0x92 = 0x00 (Read Threshold 2)
307    0x94 = 0x08 (Expire Number and Display Queue Extend)
308    0x95 = 0x11 (Extend Threshold Bit)
309    0x97 = 0x10 (LVDS Channel 2 Function Select 0)
310    0x98 = 0x00 (LVDS Channel 2 Function Select 1)
311    0x99 = 0x00 (LVDS Channel 1 Function Select 0)
312    0x9a = 0x00 (LVDS Channel 1 Function Select 1)
313    0x9b = 0x1b (Digital Video Port 1 Function Select 0)
314    0x9c = 0x00 (Digital Video Port 1 Function Select 1)
315    0x9d = 0x00 (Power Now Control 2)
316    0x9e = 0x00 (Power Now Control 3)
317    0x9f = 0x00 (Power Now Control 4)
318    0xa0 = 0x00 (Horizontal Scaling Initial Value)
319    0xa1 = 0x00 (Vertical Scaling Initial Value)
320    0xa2 = 0x00 (Horizontal and Vertical Scaling Enable)
321    0xa3 = 0x00 (Second Display Starting Address Extended)
322    0xa5 = 0x00 (Second LCD Vertical Scaling Factor)
323    0xa6 = 0x00 (Second LCD Vertical Scaling Factor)
324    0xa7 = 0x8b (Expected IGA1 Vertical Display End)
325    0xa8 = 0x01 (Expected IGA1 Vertical Display End)
326    0xa9 = 0x00 (Hardware Gamma Control)
327    0xaa = 0x00 (FIFO Depth + Threshold Overflow)
328    0xab = 0x00 (IGA2 Inetrlace Half Line)
329    0xac = 0x00 (IGA2 Inetrlace Half Line)
330    0xaf = 0x00 (P-Arbiter Write Expired Number)
331    0xb0 = 0x00 (IGA2 Pack Circuit Request Threshold)
332    0xb1 = 0x00 (IGA2 Pack Circuit Request High Threshold)
333    0xb2 = 0x00 (IGA2 Pack Circuit Request Expire Threshold)
334    0xb3 = 0x00 (IGA2 Pack Circuit Control)
335    0xb4 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
336    0xb5 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
337    0xb6 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
338    0xb7 = 0x00 (IGA2 Pack Circuit Target Base Address 0)
339    0xb8 = 0x00 (IGA2 Pack Circuit Target Line Pitch)
340    0xb9 = 0x00 (IGA2 Pack Circuit Target Line Pitch)
341    0xba = 0x00 (V Counter Set Pointer)
342    0xbb = 0x00 (V Counter Set Pointer)
343    0xbc = 0x00 (V Counter Reset Value)
344    0xbd = 0x00 (V Counter Reset Value)
345    0xbe = 0x00 (Frame Buffer Limit Value)
346    0xbf = 0x00 (Frame Buffer Limit Value)
347    0xc0 = 0x00 (Expected IGA1 Vertical Display End 1)
348    0xc1 = 0x00 (Expected IGA1 Vertical Display End 1)
349    0xc2 = 0x00 (Third LCD Vertical Scaling Factor)
350    0xc3 = 0x00 (Third LCD Vertical Scaling Factor)
351    0xc4 = 0x00 (Expected IGA1 Vertical Display End 2)
352    0xc5 = 0x00 (Expected IGA1 Vertical Display End 2)
353    0xc7 = 0x00 (Fourth LCD Vertical Scaling Factor)
354    0xc8 = 0x00 (IGA2 Pack Circuit Target Base Address 1)
355    0xc9 = 0x00 (IGA2 Pack Circuit Target Base Address 1)
356    0xca = 0x00 (IGA2 Pack Circuit Target Base Address 1)
357    0xcb = 0x00 (IGA2 Pack Circuit Target Base Address 1)
358    0xd0 = 0x00 (LVDS PLL1 Control)
359    0xd1 = 0x00 (LVDS PLL2 Control)
360    0xd2 = 0xc8 (LVDS Control)
361    0xd3 = 0x00 (LVDS Second Power Sequence Control 0)
362    0xd4 = 0x00 (LVDS Second Power Sequence Control 1)
363    0xd5 = 0x00 (LVDS Texting Mode Control)
364    0xd6 = 0x00 (DCVI Control Register 0)
365    0xd7 = 0x00 (DCVI Control Register 1)
366    0xd9 = 0x00 (Scaling Down Source Data Offset Control)
367    0xda = 0x00 (Scaling Down Source Data Offset Control)
368    0xdb = 0x00 (Scaling Down Source Data Offset Control)
369    0xdc = 0x00 (Scaling Down Vertical Scale Control)
370    0xdd = 0x00 (Scaling Down Vertical Scale Control)
371    0xde = 0x00 (Scaling Down Vertical Scale Control)
372    0xdf = 0x00 (Scaling Down Vertical Scale Control)
373    0xe0 = 0x00 (Scaling Down Destination FB Starting Addr 0)
374    0xe1 = 0x00 (Scaling Down Destination FB Starting Addr 0)
375    0xe2 = 0x00 (Scaling Down Destination FB Starting Addr 0)
376    0xe3 = 0x00 (Scaling Down Destination FB Starting Addr 0)
377    0xe4 = 0x00 (Scaling Down SW Source FB Stride)
378    0xe5 = 0x00 (Scaling Down Destination FB Starting Addr 1)
379    0xe6 = 0x00 (Scaling Down Destination FB Starting Addr 1)
380    0xe7 = 0x00 (Scaling Down Destination FB Starting Addr 1)
381    0xe8 = 0x40 (Scaling Down Destination FB Starting Addr 1)
382    0xe9 = 0x00 (Scaling Down Destination FB Starting Addr 2)
383    0xea = 0x00 (Scaling Down Destination FB Starting Addr 2)
384    0xeb = 0x00 (Scaling Down Destination FB Starting Addr 2)
385    0xec = 0x00 (IGA1 Down Scaling Destination Control)
386    0xf0 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
387    0xf1 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
388    0xf2 = 0x00 (Snapshot Mode - Starting Address of Disp Data)
389    0xf3 = 0x80 (Snapshot Mode Control)
390    0xf4 = 0x00 (Snapshot Mode Control)
391    0xf5 = 0x00 (Snapshot Mode Control)
392    0xf6 = 0x00 (Snapshot Mode Control)
393
394SL in System memory: 0x1c000000, RTSF in SL: 0x0
395Primary Display:
396    H total=1264, active=1200, blank (1200-240), sync(1208-216)
397    V total=144, active=1, blank (1-1), sync(0-0)
398base_addr=0x00000000, bpp=8
399
400Secondary Display:
401    H total=1240, active=1200, blank (1200-1240), sync(1206-190)
402    V total=912, active=900, blank (900-912), sync(904-14)
403base_addr=0x00000000, bpp=32
404
405Panel Scaling disabled
406
407LVDS Seq Mode: LVDS1 + LVDS2
408LVDS CRT Mode: LVDS1 + LVDS2
409LVDS Channel 1 Format SPWG, Power Down
410LVDS Channel 2 Format SPWG, Power Down
411
412VCK PLL: dm=596, dtx=2, dr=2, dn=1 VCK Fvco=2854054 kHz, Fout=713513 kHz
413ECK PLL: dm=633, dtx=0, dr=1, dn=2 ECK Fvco=2272982 kHz, Fout=1136491 kHz
414LDCK PLL: dm=159, dtx=2, dr=1, dn=2 LDCK Fvco=576299 kHz, Fout=288149 kHz
415000.00 = 0x00