| 1 | via-chrome-tool (C) 2009 by VIA Technologies, Inc. |
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| 2 | This is FREE SOFTWARE with ABSOLUTELY NO WARRANTY |
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| 3 | |
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| 4 | Sequencer register dump: |
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| 5 | 0x00 = 0x00 (Reset) |
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| 6 | 0x01 = 0x01 (Clocking Mode) |
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| 7 | 0x02 = 0x0f (Map Mask) |
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| 8 | 0x03 = 0x00 (Character Map Select) |
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| 9 | 0x04 = 0x06 (Memory Mode) |
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| 10 | 0x10 = 0x01 (Extended Register Unlock) |
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| 11 | 0x11 = 0x78 (Configuration 0) |
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| 12 | 0x12 = 0x00 (Configuration 1) |
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| 13 | 0x13 = 0x00 (Configuration 2 (DVP1 strapping)) |
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| 14 | 0x14 = 0x00 (Frame Buffer Size Control) |
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| 15 | 0x15 = 0x00 (Display Mode Control) |
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| 16 | 0x16 = 0x60 (Display FIFO Threshold Control) |
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| 17 | 0x17 = 0x1f (Display FIFO Control) |
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| 18 | 0x18 = 0x4e (Display Arbiter Control 0) |
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| 19 | 0x19 = 0x7f (Power Management) |
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| 20 | 0x01 CPU Interface Clock Control: 0x01 |
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| 21 | 0x02 Display Interface Clock Control: 0x02 |
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| 22 | 0x04 MC Interface Clock Control: 0x04 |
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| 23 | 0x08 Typical Arbiter Interface Clock Control: 0x08 |
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| 24 | 0x10 AGP Interface Clock Control: 0x10 |
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| 25 | 0x20 P-Arbiter Interface Clock Control: 0x20 |
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| 26 | 0x40 MIU/AGP Interface Clock Control: 0x40 |
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| 27 | 0x1a = 0x30 (PCI Bus Control) |
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| 28 | 0x1b = 0xf0 (Power Management Control 0) |
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| 29 | 0x01 Primary Display's LUT Off: 0x00 |
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| 30 | 0x18 Primary Display Engine VCK Gating: 0x10 |
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| 31 | 0x60 Secondary Display Engine LCK Gating: 0x60 |
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| 32 | 0x1c = 0x00 (Horizontal Display Fetch Count Data) |
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| 33 | 0x1d = 0x00 (Horizontal Display Fetch Count Control) |
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| 34 | 0x1e = 0xf1 (Power Management Control) |
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| 35 | 0x01 ROC ECK: 0x01 |
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| 36 | 0x02 Replace ECK by MCK: 0x00 |
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| 37 | 0x08 Spread Spectrum: 0x00 |
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| 38 | 0x30 DVP1 Power Control: 0x30 |
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| 39 | 0xc0 VCP Power Control: 0xc0 |
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| 40 | 0x20 = 0x00 (Typical Arbiter Control 0) |
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| 41 | 0x21 = 0x18 (Typical Arbiter Control 1) |
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| 42 | 0x22 = 0x14 (Display Arbiter Control 1) |
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| 43 | 0x26 = 0x3d (IIC Serial Port Control 0) |
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| 44 | 0x2a = 0x0c (Power Management Control 5) |
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| 45 | 0x03 LVDS Channel 1 Pad Control: 0x00 |
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| 46 | 0x0c LVDS Channel 2 Pad Control: 0x0c |
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| 47 | 0x40 Sprad Spectrum Type FIFO: 0x00 |
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| 48 | 0x2b = 0x00 (LVDS Interrupt Control) |
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| 49 | 0x01 MSI Pending IRQ Re-trigger: 0x00 |
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| 50 | 0x02 CRT Hot Plug Detect Enable: 0x00 |
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| 51 | 0x04 CRT Sense IRQ status: 0x00 |
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| 52 | 0x08 CRT Sense IRQ enable: 0x00 |
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| 53 | 0x10 LVDS Sense IRQ status: 0x00 |
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| 54 | 0x20 LVDS Sense IRQ enable: 0x00 |
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| 55 | 0x2c = 0xc2 (General Purpose I/O Port) |
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| 56 | 0x2d = 0xff (Power Management Control 1) |
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| 57 | 0x03 ECK Pll Power Control: 0x03 |
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| 58 | 0x0c LCK PLL Power Control: 0x0c |
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| 59 | 0x30 VCK PLL Powre Control: 0x30 |
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| 60 | 0xc0 E3_ECK_N Selection: 0xc0 |
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| 61 | 0x2e = 0xff (Power Management Control 2) |
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| 62 | 0x03 Video Playback Engine V3/V4 Gated Clock VCK: 0x03 |
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| 63 | 0x0c PCI Master / DMA Gated Clock ECK/CPUCK: 0x0c |
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| 64 | 0x30 Video Processor Gated Clock ECK: 0x30 |
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| 65 | 0xc0 Capturer Gated Clock ECK: 0xc0 |
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| 66 | 0x31 = 0x00 (IIC Serial Port Control 1) |
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| 67 | 0x35 = 0x2d (Subsystem Vendor ID Low) |
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| 68 | 0x36 = 0x15 (Subsystem Vendor ID High) |
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| 69 | 0x37 = 0x33 (Subsystem ID Low) |
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| 70 | 0x38 = 0x08 (Subsystem ID High) |
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| 71 | 0x39 = 0x10 (BIOS Reserved Register 0) |
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| 72 | 0x3a = 0x00 (BIOS Reserved Register 1) |
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| 73 | 0x3b = 0x01 (PCI Revision ID Back Door) |
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| 74 | 0x3c = 0x1d (Miscellaneous) |
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| 75 | 0x01 AGP Bus Pack Door AGP3 Enable: 0x01 |
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| 76 | 0x02 Switch 3 PLLs to Prime Output: 0x00 |
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| 77 | 0x04 LCDCK PLL Locked Detect: 0x04 |
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| 78 | 0x08 VCK PLL Locked Detect: 0x08 |
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| 79 | 0x10 ECL PLL Locked Detect: 0x10 |
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| 80 | 0x60 PLL Frequency Division Select for Testing: 0x00 |
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| 81 | 0x3d = 0x06 (General Purpose I/O Port) |
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| 82 | 0x3e = 0x20 (Miscellaneous Register for AGP Mux) |
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| 83 | 0x3f = 0xff (Power Management Control 2) |
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| 84 | 0x03 Video Clock Control (Gated ECK): 0x03 |
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| 85 | 0x0c 2D Clock Control (Gated ECK/CPUCK): 0x0c |
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| 86 | 0x30 3D Clock Control (Gated ECK): 0x30 |
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| 87 | 0xc0 CR Clock Control (Gated ECK): 0xc0 |
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| 88 | 0x40 = 0x00 (PLL Control) |
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| 89 | 0x01 Reset ECK PLL: 0x00 |
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| 90 | 0x02 Reset VCK PLL: 0x00 |
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| 91 | 0x04 Reset LCDCK PLL: 0x00 |
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| 92 | 0x08 LVDS Interrupt Method: 0x00 |
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| 93 | 0x30 Free Run ECK Frequency within Idle Mode: 0x00 |
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| 94 | 0x80 CRT Sense Enable: 0x00 |
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| 95 | 0x41 = 0xb0 (Typical Arbiter Control 1) |
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| 96 | 0x42 = 0x10 (Typical Arbiter Control 1) |
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| 97 | 0x43 = 0xff (Graphics Bonding Option) |
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| 98 | 0x01 Notebook Used Flag: 0x01 |
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| 99 | 0x04 Typical Channel 1 Arbiter Read Back Data Overwrite Flag: 0x04 |
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| 100 | 0x08 Typical Channel 0 Arbiter Read Back Data Overwrite Flag: 0x08 |
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| 101 | 0x10 IGA1 Display FIFO Underflow Flag: 0x10 |
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| 102 | 0x20 IGA2 Dispaly FIFO Underflow Flag: 0x20 |
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| 103 | 0x40 Windows Media Video Enable Flag: 0x40 |
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| 104 | 0x80 Advance Video Enable Flag: 0x80 |
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| 105 | 0x44 = 0x54 (VCK Clock Synthesizer Vallue 0) |
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| 106 | 0x45 = 0x90 (VCK Clock Synthesizer Vallue 1) |
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| 107 | 0x46 = 0x03 (VCK Clock Synthesizer Vallue 2) |
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| 108 | 0x47 = 0x79 (ECK Clock Synthesizer Vallue 0) |
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| 109 | 0x48 = 0x88 (ECK Clock Synthesizer Vallue 1) |
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| 110 | 0x49 = 0x04 (ECK Clock Synthesizer Vallue 2) |
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| 111 | 0x4a = 0x9f (LDCK Clock Synthesizer Value 0) |
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| 112 | 0x4b = 0x0c (LDCK Clock Synthesizer Value 1) |
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| 113 | 0x4c = 0x05 (LDCK Clock Synthesizer Value 2) |
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| 114 | 0x4d = 0x30 (Preemptive Arbiter Control) |
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| 115 | 0x4e = 0x00 (Software Reset Control) |
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| 116 | 0x4f = 0x5f (CR Gating Clock Control) |
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| 117 | 0x50 = 0x1f (AGP Control) |
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| 118 | 0x51 = 0x81 (Display FIFO Control 1) |
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| 119 | 0x52 = 0x00 (Integrated TV Shadow Register Control) |
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| 120 | 0x53 = 0xff (DAC Sense Control 1) |
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| 121 | 0x54 = 0x00 (DAC Sense Control 2) |
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| 122 | 0x55 = 0x00 (DAC Sense Control 3) |
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| 123 | 0x56 = 0xff (DAC Sense Control 4) |
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| 124 | 0x57 = 0x00 (Display FIFO Control 2) |
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| 125 | 0x58 = 0x08 (GFX Power Control 1) |
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| 126 | 0x59 = 0xdf (GFX Power Control 2) |
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| 127 | 0x01 GFX-NM AGP Dynamic Clock Enable: 0x01 |
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| 128 | 0x02 GFX-NM GMINT Channel 0 Dynamic Clock Enable: 0x02 |
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| 129 | 0x04 GFX-NM GMINT Channel 1 Dynamic Clock Enable: 0x04 |
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| 130 | 0x08 GFX-NM PCIC Dynamic Clock Enable: 0x08 |
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| 131 | 0x10 GFX-NM IGA Dynamic Clock Enable: 0x10 |
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| 132 | 0x20 IGA Low Thrshold Enable: 0x00 |
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| 133 | 0x80 IGA1 Enable: 0x80 |
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| 134 | 0x5a = 0x00 (PCI Bus Control 2) |
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| 135 | 0x5b = 0x51 (Device Used Status 0) |
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| 136 | 0x01 LVDS1 Used IGA2 Source: 0x01 |
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| 137 | 0x02 LBDS1 Used IGA1 Source: 0x00 |
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| 138 | 0x04 LVDS0 Used IGA2 Source: 0x00 |
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| 139 | 0x08 LVDS1 Used IGA1 Source: 0x00 |
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| 140 | 0x10 DAC0 Used IGA2 Source: 0x10 |
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| 141 | 0x20 DAC0 Used IGA1 Source: 0x00 |
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| 142 | 0x40 DAC0 User is TV: 0x40 |
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| 143 | 0x80 DCVI Source Selection is TV: 0x00 |
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| 144 | 0x5c = 0x29 (Device Used Status 1) |
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| 145 | 0x01 DVP1 Used IGA2 Source: 0x01 |
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| 146 | 0x02 DVP1 Used IGA1 Source: 0x00 |
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| 147 | 0x10 DAC1 Used IGA2 Source: 0x00 |
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| 148 | 0x20 DAC1 Used IGA1 Source: 0x20 |
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| 149 | 0x40 DAC1 User is TV: 0x00 |
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| 150 | 0x5d = 0x00 (Timer Control) |
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| 151 | 0x5e = 0x00 (DAC Control 2) |
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| 152 | 0x60 = 0x00 (I2C Mode Control) |
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| 153 | 0x61 = 0x00 (I2C Host Address) |
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| 154 | 0x62 = 0x00 (I2C Host Data) |
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| 155 | 0x63 = 0x00 (I2C Host Control) |
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| 156 | 0x64 = 0x20 (I2C Status) |
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| 157 | 0x65 = 0x00 (Power Management Control 6) |
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| 158 | 0x66 = 0x20 (GTI Control 0) |
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| 159 | 0x67 = 0x20 (GTI Control 1) |
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| 160 | 0x68 = 0xe0 (GTI Control 1) |
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| 161 | 0x69 = 0x20 (GTI Control 1) |
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| 162 | 0x6a = 0x00 (GTI Control 1) |
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| 163 | 0x6b = 0x00 (GTI Control 1) |
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| 164 | 0x6c = 0x00 (GTI Control 1) |
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| 165 | 0x6d = 0xe0 (GTI Control 1) |
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| 166 | 0x6e = 0x01 (GTI Control 1) |
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| 167 | 0x6f = 0x00 (GTI Control 1) |
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| 168 | 0x70 = 0x20 (GARB Control 0) |
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| 169 | 0x71 = 0x04 (Typical Arbiter Control 2) |
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| 170 | 0x72 = 0x0f (Typical Arbiter Control 3) |
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| 171 | 0x73 = 0x33 (Typical Arbiter Control 4) |
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| 172 | 0x74 = 0x1f (Typical Arbiter Control 5) |
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| 173 | 0x75 = 0x1f (Typical Arbiter Control 6) |
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| 174 | 0x76 = 0x00 (Backlight Control 1) |
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| 175 | 0x01 Backlight Control Enable: 0x00 |
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| 176 | 0x77 = 0x00 (Backlight Control 2) |
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| 177 | 0x78 = 0x60 (Backlight Control 3) |
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| 178 | |
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| 179 | Graphic Controller register dump: |
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| 180 | 0x00 = 0x00 (Set / Reset) |
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| 181 | 0x01 = 0x00 (Enable Set / Reset) |
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| 182 | 0x02 = 0x00 (Color Compare) |
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| 183 | 0x03 = 0x00 (Data Rotate) |
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| 184 | 0x04 = 0x00 (Read Map Select) |
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| 185 | 0x05 = 0x00 (Mode) |
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| 186 | 0x06 = 0x00 (Miscellaneous) |
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| 187 | 0x07 = 0x00 (Color Don't Care) |
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| 188 | 0x08 = 0x00 (Bit Mask) |
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| 189 | 0x20 = 0x00 (Offset Register Control) |
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| 190 | 0x21 = 0x00 (Offset Register A) |
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| 191 | 0x22 = 0x00 (Offset Register B) |
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| 192 | |
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| 193 | CRT controller register dump: |
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| 194 | 0x00 = 0x99 (Horizontal Total) |
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| 195 | 0x01 = 0x95 (Horizontal Display End) |
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| 196 | 0x02 = 0x95 (Start Horizontal Blank) |
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| 197 | 0x03 = 0x9d (End Horizontal Blank) |
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| 198 | 0x04 = 0x97 (Start Horizontal Retrace) |
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| 199 | 0x05 = 0x1b (End Horizontal Retrace) |
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| 200 | 0x06 = 0x8e (Vertical Total) |
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| 201 | 0x07 = 0x00 (Overflow) |
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| 202 | 0x08 = 0x00 (Preset Row Scan) |
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| 203 | 0x09 = 0x00 (Max Scan Line) |
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| 204 | 0x0a = 0x00 (Cursor Start) |
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| 205 | 0x0b = 0x00 (Cursor End) |
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| 206 | 0x0c = 0x00 (Start Address High) |
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| 207 | 0x0d = 0x00 (Start Address Low) |
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| 208 | 0x0e = 0x00 (Cursor Location High) |
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| 209 | 0x0f = 0x00 (Cursor Location Low) |
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| 210 | 0x10 = 0x00 (Vertical Retrace Start) |
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| 211 | 0x11 = 0x00 (Vertical Retrace End) |
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| 212 | 0x12 = 0x00 (Vertical Display End) |
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| 213 | 0x13 = 0x00 (Offset) |
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| 214 | 0x14 = 0x00 (Underline Location) |
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| 215 | 0x15 = 0x00 (Start Vertical Blank) |
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| 216 | 0x16 = 0x00 (End Vertical Blank) |
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| 217 | 0x17 = 0xa3 (CRTC Mode Control) |
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| 218 | 0x18 = 0x00 (Line Compare) |
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| 219 | 0x30 = 0x08 (Display Fetch Blocking Control) |
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| 220 | 0x31 = 0x00 (Half Line Position) |
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| 221 | 0x32 = 0x11 (Mode Control) |
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| 222 | 0x33 = 0x00 (Hsync Adjuster) |
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| 223 | 0x34 = 0x00 (Starting Address Overflow) |
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| 224 | 0x35 = 0x00 (Extended Overflow) |
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| 225 | 0x36 = 0x01 (Power Management Control 3) |
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| 226 | 0x37 = 0x34 (DAC Control) |
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| 227 | 0x38 = 0xdc (Signature Data B0) |
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| 228 | 0x39 = 0x4a (Signature Data B1) |
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| 229 | 0x3a = 0x0d (Signature Data B2) |
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| 230 | 0x3b = 0x01 (Scratch Pad 2) |
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| 231 | 0x3c = 0x08 (Scratch Pad 3) |
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| 232 | 0x3d = 0x64 (Scratch Pad 4) |
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| 233 | 0x3e = 0x20 (Scratch Pad 5) |
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| 234 | 0x3f = 0x0b (Scratch Pad 6) |
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| 235 | 0x40 = 0x00 (Test Mode Control 0) |
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| 236 | 0x43 = 0x80 (IGA1 Display Control) |
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| 237 | 0x45 = 0x00 (Power Now Indicator Control 3) |
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| 238 | 0x46 = 0x00 (Test Mode Control 1) |
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| 239 | 0x47 = 0x00 (Test Mode Control 2) |
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| 240 | 0x48 = 0x00 (Starting Address Overflow) |
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| 241 | 0x50 = 0xd7 (Second CRTC Horizontal Total Period) |
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| 242 | 0x51 = 0xaf (Second CRTC Horizontal Active Data Period) |
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| 243 | 0x52 = 0xaf (Second CRTC Horizontal Blanking Start) |
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| 244 | 0x53 = 0xd7 (Second CRTC Horizontal Blanking End) |
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| 245 | 0x54 = 0x24 (Second CRTC Horizontal Blanking Overflow) |
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| 246 | 0x55 = 0x44 (Second CRTC Horizontal Period Overflow) |
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| 247 | 0x56 = 0xb6 (Second CRTC Horizontal Retrace Start) |
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| 248 | 0x57 = 0xbe (Second CRTC Horizontal Retrace End) |
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| 249 | 0x58 = 0x8f (Second CRTC Vertical Total Period) |
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| 250 | 0x59 = 0x83 (Second CRTC Vertical Active Data Period) |
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| 251 | 0x5a = 0x83 (Second CRTC Vertical Blanking Start) |
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| 252 | 0x5b = 0x8f (Second CRTC Vertical Blanking End) |
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| 253 | 0x5c = 0x9b (Second CRTC Vertical Blanking Overflow) |
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| 254 | 0x5d = 0x1b (Second CRTC Vertical Period Overflow) |
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| 255 | 0x5e = 0x88 (Second CRTC Vertical Retrace Start) |
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| 256 | 0x5f = 0x6e (Second CRTC Vertical Retrace End) |
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| 257 | 0x60 = 0x46 (Second CRTC Vertical Status 1) |
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| 258 | 0x61 = 0x52 (Second CRTC Vertical Status 2) |
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| 259 | 0x62 = 0x00 (Second Display Starting Address Low) |
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| 260 | 0x63 = 0x00 (Second Display Starting Address Middle) |
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| 261 | 0x64 = 0x00 (Second Display Starting Address High) |
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| 262 | 0x65 = 0x2c (Second Display Horizontal Quadword Count) |
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| 263 | 0x66 = 0x58 (Second Display Horizontal Offset) |
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| 264 | 0x67 = 0xd6 (Second Display Col Depth and Horiz Overfl) |
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| 265 | 0x68 = 0xf0 (Second Display Queue Depth and Read Thresh) |
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| 266 | 0x69 = 0x00 (Second Display Interrupt Enable and Status) |
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| 267 | 0x6a = 0xc8 (Second Display Channel and LCD Enable) |
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| 268 | 0x6b = 0x00 (Channel 1 and 2 Clock Mode Selection) |
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| 269 | 0x6c = 0x00 (TV Clock Control) |
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| 270 | 0x6d = 0xff (Horizontal Total Shadow) |
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| 271 | 0x6e = 0x77 (End Horizontal Blanking Shadow) |
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| 272 | 0x6f = 0xef (Vertical Total Shadow) |
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| 273 | 0x70 = 0x7f (Vertical Display Enable End Shadow) |
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| 274 | 0x71 = 0x7f (Vertical Display Overflow Shadow) |
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| 275 | 0x72 = 0x2f (Start Vertical Blank Shadow) |
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| 276 | 0x73 = 0xef (End Vertical Blank Shadow) |
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| 277 | 0x74 = 0xe7 (Vertical Blank Overflow Shadow) |
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| 278 | 0x75 = 0xee (Vertical Retrace Start Shadow) |
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| 279 | 0x76 = 0x77 (Vertical Retrace End Shadow) |
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| 280 | 0x77 = 0x00 (LCD Horizontal Scaling Factor) |
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| 281 | 0x78 = 0x6f (LCD Vertical Scaling Facor) |
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| 282 | 0x79 = 0x68 (LCD Scaling Control) |
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| 283 | 0x7a = 0x01 (LCD Scaling Parameter 1) |
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| 284 | 0x7b = 0x02 (LCD Scaling Parameter 2) |
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| 285 | 0x7c = 0x03 (LCD Scaling Parameter 3) |
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| 286 | 0x7d = 0x04 (LCD Scaling Parameter 4) |
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| 287 | 0x7e = 0x07 (LCD Scaling Parameter 5) |
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| 288 | 0x7f = 0x0a (LCD Scaling Parameter 6) |
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| 289 | 0x80 = 0x0d (LCD Scaling Parameter 7) |
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| 290 | 0x81 = 0x13 (LCD Scaling Parameter 8) |
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| 291 | 0x82 = 0x16 (LCD Scaling Parameter 9) |
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| 292 | 0x83 = 0x19 (LCD Scaling Parameter 10) |
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| 293 | 0x84 = 0x1c (LCD Scaling Parameter 11) |
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| 294 | 0x85 = 0x1d (LCD Scaling Parameter 12) |
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| 295 | 0x86 = 0x1e (LCD Scaling Parameter 13) |
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| 296 | 0x87 = 0x1f (LCD Scaling Parameter 14) |
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| 297 | 0x88 = 0x60 (LCD Panel Type) |
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| 298 | 0x8a = 0x01 (LCD Timing Control 1) |
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| 299 | 0x8b = 0xca (LCD Power Sequence Control 0) |
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| 300 | 0x8c = 0xca (LCD Power Sequence Control 1) |
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| 301 | 0x8d = 0xca (LCD Power Sequence Control 2) |
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| 302 | 0x8e = 0xca (LCD Power Sequence Control 3) |
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| 303 | 0x8f = 0x11 (LCD Power Sequence Control 4) |
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| 304 | 0x90 = 0x11 (LCD Power Sequence Control 5) |
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| 305 | 0x91 = 0x00 (Software Cotnrol Power Sequence) |
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| 306 | 0x92 = 0x00 (Read Threshold 2) |
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| 307 | 0x94 = 0x08 (Expire Number and Display Queue Extend) |
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| 308 | 0x95 = 0x11 (Extend Threshold Bit) |
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| 309 | 0x97 = 0x10 (LVDS Channel 2 Function Select 0) |
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| 310 | 0x98 = 0x00 (LVDS Channel 2 Function Select 1) |
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| 311 | 0x99 = 0x00 (LVDS Channel 1 Function Select 0) |
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| 312 | 0x9a = 0x00 (LVDS Channel 1 Function Select 1) |
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| 313 | 0x9b = 0x1b (Digital Video Port 1 Function Select 0) |
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| 314 | 0x9c = 0x00 (Digital Video Port 1 Function Select 1) |
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| 315 | 0x9d = 0x00 (Power Now Control 2) |
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| 316 | 0x9e = 0x00 (Power Now Control 3) |
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| 317 | 0x9f = 0x00 (Power Now Control 4) |
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| 318 | 0xa0 = 0x00 (Horizontal Scaling Initial Value) |
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| 319 | 0xa1 = 0x00 (Vertical Scaling Initial Value) |
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| 320 | 0xa2 = 0x00 (Horizontal and Vertical Scaling Enable) |
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| 321 | 0xa3 = 0x00 (Second Display Starting Address Extended) |
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| 322 | 0xa5 = 0x00 (Second LCD Vertical Scaling Factor) |
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| 323 | 0xa6 = 0x00 (Second LCD Vertical Scaling Factor) |
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| 324 | 0xa7 = 0x8b (Expected IGA1 Vertical Display End) |
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| 325 | 0xa8 = 0x01 (Expected IGA1 Vertical Display End) |
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| 326 | 0xa9 = 0x00 (Hardware Gamma Control) |
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| 327 | 0xaa = 0x00 (FIFO Depth + Threshold Overflow) |
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| 328 | 0xab = 0x00 (IGA2 Inetrlace Half Line) |
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| 329 | 0xac = 0x00 (IGA2 Inetrlace Half Line) |
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| 330 | 0xaf = 0x00 (P-Arbiter Write Expired Number) |
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| 331 | 0xb0 = 0x00 (IGA2 Pack Circuit Request Threshold) |
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| 332 | 0xb1 = 0x00 (IGA2 Pack Circuit Request High Threshold) |
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| 333 | 0xb2 = 0x00 (IGA2 Pack Circuit Request Expire Threshold) |
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| 334 | 0xb3 = 0x00 (IGA2 Pack Circuit Control) |
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| 335 | 0xb4 = 0x00 (IGA2 Pack Circuit Target Base Address 0) |
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| 336 | 0xb5 = 0x00 (IGA2 Pack Circuit Target Base Address 0) |
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| 337 | 0xb6 = 0x00 (IGA2 Pack Circuit Target Base Address 0) |
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| 338 | 0xb7 = 0x00 (IGA2 Pack Circuit Target Base Address 0) |
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| 339 | 0xb8 = 0x00 (IGA2 Pack Circuit Target Line Pitch) |
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| 340 | 0xb9 = 0x00 (IGA2 Pack Circuit Target Line Pitch) |
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| 341 | 0xba = 0x00 (V Counter Set Pointer) |
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| 342 | 0xbb = 0x00 (V Counter Set Pointer) |
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| 343 | 0xbc = 0x00 (V Counter Reset Value) |
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| 344 | 0xbd = 0x00 (V Counter Reset Value) |
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| 345 | 0xbe = 0x00 (Frame Buffer Limit Value) |
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| 346 | 0xbf = 0x00 (Frame Buffer Limit Value) |
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| 347 | 0xc0 = 0x00 (Expected IGA1 Vertical Display End 1) |
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| 348 | 0xc1 = 0x00 (Expected IGA1 Vertical Display End 1) |
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| 349 | 0xc2 = 0x00 (Third LCD Vertical Scaling Factor) |
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| 350 | 0xc3 = 0x00 (Third LCD Vertical Scaling Factor) |
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| 351 | 0xc4 = 0x00 (Expected IGA1 Vertical Display End 2) |
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| 352 | 0xc5 = 0x00 (Expected IGA1 Vertical Display End 2) |
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| 353 | 0xc7 = 0x00 (Fourth LCD Vertical Scaling Factor) |
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| 354 | 0xc8 = 0x00 (IGA2 Pack Circuit Target Base Address 1) |
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| 355 | 0xc9 = 0x00 (IGA2 Pack Circuit Target Base Address 1) |
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| 356 | 0xca = 0x00 (IGA2 Pack Circuit Target Base Address 1) |
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| 357 | 0xcb = 0x00 (IGA2 Pack Circuit Target Base Address 1) |
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| 358 | 0xd0 = 0x00 (LVDS PLL1 Control) |
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| 359 | 0xd1 = 0x00 (LVDS PLL2 Control) |
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| 360 | 0xd2 = 0xc8 (LVDS Control) |
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| 361 | 0xd3 = 0x00 (LVDS Second Power Sequence Control 0) |
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| 362 | 0xd4 = 0x00 (LVDS Second Power Sequence Control 1) |
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| 363 | 0xd5 = 0x00 (LVDS Texting Mode Control) |
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| 364 | 0xd6 = 0x00 (DCVI Control Register 0) |
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| 365 | 0xd7 = 0x00 (DCVI Control Register 1) |
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| 366 | 0xd9 = 0x00 (Scaling Down Source Data Offset Control) |
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| 367 | 0xda = 0x00 (Scaling Down Source Data Offset Control) |
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| 368 | 0xdb = 0x00 (Scaling Down Source Data Offset Control) |
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| 369 | 0xdc = 0x00 (Scaling Down Vertical Scale Control) |
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| 370 | 0xdd = 0x00 (Scaling Down Vertical Scale Control) |
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| 371 | 0xde = 0x00 (Scaling Down Vertical Scale Control) |
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| 372 | 0xdf = 0x00 (Scaling Down Vertical Scale Control) |
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| 373 | 0xe0 = 0x00 (Scaling Down Destination FB Starting Addr 0) |
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| 374 | 0xe1 = 0x00 (Scaling Down Destination FB Starting Addr 0) |
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| 375 | 0xe2 = 0x00 (Scaling Down Destination FB Starting Addr 0) |
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| 376 | 0xe3 = 0x00 (Scaling Down Destination FB Starting Addr 0) |
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| 377 | 0xe4 = 0x00 (Scaling Down SW Source FB Stride) |
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| 378 | 0xe5 = 0x00 (Scaling Down Destination FB Starting Addr 1) |
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| 379 | 0xe6 = 0x00 (Scaling Down Destination FB Starting Addr 1) |
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| 380 | 0xe7 = 0x00 (Scaling Down Destination FB Starting Addr 1) |
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| 381 | 0xe8 = 0x40 (Scaling Down Destination FB Starting Addr 1) |
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| 382 | 0xe9 = 0x00 (Scaling Down Destination FB Starting Addr 2) |
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| 383 | 0xea = 0x00 (Scaling Down Destination FB Starting Addr 2) |
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| 384 | 0xeb = 0x00 (Scaling Down Destination FB Starting Addr 2) |
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| 385 | 0xec = 0x00 (IGA1 Down Scaling Destination Control) |
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| 386 | 0xf0 = 0x00 (Snapshot Mode - Starting Address of Disp Data) |
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| 387 | 0xf1 = 0x00 (Snapshot Mode - Starting Address of Disp Data) |
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| 388 | 0xf2 = 0x00 (Snapshot Mode - Starting Address of Disp Data) |
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| 389 | 0xf3 = 0x80 (Snapshot Mode Control) |
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| 390 | 0xf4 = 0x00 (Snapshot Mode Control) |
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| 391 | 0xf5 = 0x00 (Snapshot Mode Control) |
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| 392 | 0xf6 = 0x00 (Snapshot Mode Control) |
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| 393 | |
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| 394 | SL in System memory: 0x1c000000, RTSF in SL: 0x0 |
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| 395 | Primary Display: |
|---|
| 396 | H total=1264, active=1200, blank (1200-240), sync(1208-216) |
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| 397 | V total=144, active=1, blank (1-1), sync(0-0) |
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| 398 | base_addr=0x00000000, bpp=8 |
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| 399 | |
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| 400 | Secondary Display: |
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| 401 | H total=1240, active=1200, blank (1200-1240), sync(1206-190) |
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| 402 | V total=912, active=900, blank (900-912), sync(904-14) |
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| 403 | base_addr=0x00000000, bpp=32 |
|---|
| 404 | |
|---|
| 405 | Panel Scaling disabled |
|---|
| 406 | |
|---|
| 407 | LVDS Seq Mode: LVDS1 + LVDS2 |
|---|
| 408 | LVDS CRT Mode: LVDS1 + LVDS2 |
|---|
| 409 | LVDS Channel 1 Format SPWG, Power Down |
|---|
| 410 | LVDS Channel 2 Format SPWG, Power Down |
|---|
| 411 | |
|---|
| 412 | VCK PLL: dm=596, dtx=2, dr=2, dn=1 VCK Fvco=2854054 kHz, Fout=713513 kHz |
|---|
| 413 | ECK PLL: dm=633, dtx=0, dr=1, dn=2 ECK Fvco=2272982 kHz, Fout=1136491 kHz |
|---|
| 414 | LDCK PLL: dm=159, dtx=2, dr=1, dn=2 LDCK Fvco=576299 kHz, Fout=288149 kHz |
|---|
| 415 | 000.00 = 0x00 |
|---|
