Ticket #11918 (closed defect: fixed)
Nanya/Micron 2Gb DRAM doesn't work
| Reported by: | wad | Owned by: | Quozl |
|---|---|---|---|
| Priority: | normal | Milestone: | 1.75-firmware |
| Component: | ofw - open firmware | Version: | 1.75-C1 |
| Keywords: | XO-1.75 | Cc: | wad, quozl, wmb@… |
| Action Needed: | never set | Verified: | no |
| Deployments affected: | Blocked By: | ||
| Blocking: |
Description
When testing the latest 2Gb DD3 die from Nanya (NT5CB256M8GN-CG), which is also shipped as Micron's MT4J256M8HX-15E, memory errors prevented a current OFW from booting.
Further examination showed that our existing memory timing is not valid for those parts. Per JEDEC JESD-79-3D ( http://www.jedec.org/standards-documents/docs/jesd-79-3d ), 2Gb parts are allowed to have a longer tRFC than used by our current timing.
We haven't seen a problem with already qualified 2Gb parts, but those will probably be EOL'd soon in favor of newer dies.
I suggest that CForth's memory configuration code be changed to include conditional setting of register 0xd0000060 to 0x64660404 (instead of 0x646602C4) when configuring 1GB of memory.
This value meets the JEDEC requirements, and has been tested to work with the Nanya memory. It appears both Micron test boards had rework problems, and haven't been tested yet.
Before releasing this modification, we should test with all qualified 2Gb parts. It is expected, however, that even 1Gb parts should work with this more conservative timing.


