Disable CPU access to EC RAM and I/O
|Reported by:||wmb@…||Owned by:||wmb@…|
|Deployments affected:||Action Needed:|
It is currently possible for the main CPU to access arbitrary EC RAM and I/O resources via the 381,382,383 I/O port dance. For security reasons, we need to disable that and provide EC commands to access specific information that we currently get via that path.
Here are some things that we current access via ports 381..383. Please add to this list as necessary:
a) Polling for game key presses in fast-boot firmware (if a game key is pressed, the interactive boot path is used)
b) Controlling write-protect for the SPI FLASH
c) Turning the keyboard controller functionality on and off for the purpose of programming SPI FLASH (there may be a new command for this already)
d) Programming the SPI FLASH.
e) Controlling the keyboard LEDs (which are going away, so this is probably moot)
f) Resetting the wireless LAN module
g) Accessing battery state information
h) Bit-banging the 1-wire battery status line for recovering bricked batteries
We may want to leave direct access available to the firmware at early system firmware startup, and then turn it off when we latch on the SPI FLASH write protect. That would let the system firmware perform SPI reflashing using the current direct access method.
Change History (22)
comment:8 Changed 10 years ago by rsmith
- Owner changed from David.Lin to rsmith
- Type changed from defect to task
comment:15 Changed 10 years ago by jg
- Milestone changed from Trial-3 to MP Start
- Owner changed from rsmith to wmb@…