Ticket #12589 (closed defect: fixed)
XO-4: second PJ4 core and MM core need to be powered off.
|Reported by:||pgf||Owned by:||Quozl|
|Component:||ofw - open firmware||Version:||Development source as of this date|
|Action Needed:||no action||Verified:||no|
|Deployments affected:||Blocked By:|
currently the two unused cores are left in reset (their default state) while the system is running.
it will save considerable power, and reduce the operating temperature, to release them from reset and power them down.
the following OFW lines accomplish this:
e320f003 0 instruction! 2000.0062 200 pmua! 2000.0062 204 pmua! 150 pmua@ 0600.0000 or 150 pmua!
the above is a distillation of this recipe from andres and mitch:
Here's the recipe for turning off cores. \ Check that all 3 cores are currently powered (bits 8,9,10) ok 90 pmua@ . 701 ok e320f003 0 instruction! \ Put a WFI in the reset vector To disable the low power core: ok 2000.0062 204 pmua! \ power down MMCore's L1, SRAM, core, and \ core clock when core enters WFI ok 150 pmua@ 0400.0000 or 150 pmua! \ unreset MMCore ok 90 pmua@ . \ check core status 3c1 \ bit 10 is now unset (MMCore powered off) To disable the second high power core (MP2): ok 2000.0062 200 pmua! \ power down MP2's L1, etc w/ WFI ok 150 pmua@ 0200.0000 or 150 pmua! \ Unreset MPCORE2 ok 90 pmua@ . \ check core status 1f1 \ bit 9 is now unset (MP2 powered off)
we should apply this (with comments) somewhere appropriate in OFW. it needn't be in cforth.