nandflash writes fail with OFW

[cjb]

This took a long time to track down. :/

dmesg attached. OFW boots the NAND flash, but writes start failing almost immediately and soon jffs2 panics. This was 100% reproducible with both usedma=1 and 0; it wasn't working for hours, I flashed from OFW back to LaB, it worked straight away.

I'm having trouble explaining it. I *wrote* the image to the nandflash inside OFW, so it's not that all writes from inside OFW are failing, but most writes are. The video output was full of things like "{chown,touch,rm}: I/O error".

[cjb]

I should be clear about my testcase:

* flash_eraseall -j /dev/mtd0
* nandwrite -p /dev/mtd0 olpc-redhat-stream-development-build-130-20061026_0003-devel_jffs2.img
* reboot

.. it will start failing shorting after "Starting udev.." and panic() before showing the login prompt.

Build 130 is at:

http://olpc.download.redhat.com/olpc/streams/development/build130/devel_jffs2/olpc-redhat-stream-development-build-130-20061026_0003-devel_jffs2.img

Since OFW can't currently boot flash unmodified, I was doing (from memory rather than scrollback):

[interrupt autoboot]
setenv boot-disk /nandflash:\boot\vmlinuz
setenv boot-file ... root=mtd0 rootfstype=jffs2 ...
boot

[wmb@…]

As David W. suspected, the problem is that the OFW driver was leaving the CaFe NAND controller in the "write protect" state. The fix was trivial - just hit the soft-reset bit in the OFW driver close routine. I've made that change.

The Linux driver really should do the soft-reset too, in its initialization, thus ensuring a predictable init no matter what state the hardware is in. This also has the advantage of making sure the DMA engine is in a clean state.

The way to perform this reset is to first write 0x01, then 0x00 to the 32-bit chip register at offset 0x3034. You can just write that bit, no need to read/modify/write.

I'm reassigning to David to get the change into Linux too.

[dwmw2]

Should be fixed in olpc-2.6 git tree. Will transfer to Fedora package later today after testing.

Thanks for the extremely coherent instructions.