VCORE Modifications

The current state of the power supplies on the A1 is very noisy, with the major component synchronous with VCORE switching. This noise was triggering the +1.8VSUS shutdown on VCORE startup, a time of maximum current draw from Vin. The noise is high frequency (1 MHz) ringing coupled through Vin onto all power supplies (3VPCU, etc.). +1.8VSUS has improved immunity due to Vin decoupling through a ferrite.

The suggested circuit modifications to minimize this noise are:

Inserting a 3.3 ohm resistor (5 ohm was used in these tests) between the BST input to the MAX1907 (PU3), to slow down the rise time of the upper MOSFET gate drive signal.
Adding a capacitor between the gate of the lower MOSFET and a quiet GND. Different values from 3300 pF to 6800 pF were tried, with the larger value performing better (but consuming more power). This decouples the gate from 1907LX signal coming through the drain-gate capacitance.
Adding a small (approx. 2.7 ohm -- 4.3 ohm was used in these traces) series resistor in the DH line, to slow down both the rising and falling edges. This should be located near PU3.
Adding a third 10 uF bypass capacitor on Vin in parallel with PC33/PC35. Perhaps even a 4.7 uF with a different resonant frequency would help ?
Adding a position for a ferrite between Vin and the bypass capacitors (PC33/PC35) and upper MOSFET (PQ11) drain.

In all figures, the display channels are assigned to the same signals. The amplitude and position of the display channels may vary from figure to figure.

Purple - +VCORE, the processor VCORE power supply, measured at PJP5. Shown at 200 mV/div unless indicated otherwise.
Green - 1907DH, the upper MOSFET gate drive, measured at the MOSFET. Shown at 10 V/div.
Yellow - 1907DL, the lower MOSFET gate drive, measured at the MOSFET. Shown at 1 V/div.
Blue - +1.8VSUS, the memory +1.8V power supply, measured at PJP3. Shown at 500 mV/div, offset by +1.8V.

VCR2: MB I w. no modifications

VCR2 is a trace from the same unmodified motherboard, taken during the startup of VCORE (high load). Here we see the induced voltage at the lower MOSFET gate exceed the Vgs conduction threshold, inducing direct Vin to ground feedthrough and triggering a noise burst that conducts 0.5+V of noise onto the (filtered) +1.8V rail, along with every other rail. VCORE shown at 500mV/div.

VCR1: MB I w. no modifications

VCR1 is a trace from the Isabel MB, unmodified except for those modifications made to all A1 motherboards during bring-up. The trace was taken while OFW was running (light VCORE load). The noise is 125 MHz ringing, with an amplitude of 0.2V on a 0.8V power rail.

Modified performance

VCM12: MB I w. suggested modifications wo. ferrite

VCM12 is a trace from the same Isabel MB, after modification, taken during startup of VCORE. The modifications were the suggested ones, except for no ferrite. The value of the low MOSFET gate decoupling capacitor was 6800 pF.

VCM7: MB I w. suggested modifications

VCM7 is a trace from the same Isabel MB, after modification, taken during VCORE startup. The modifications were the suggested ones. The value of the low MOSFET gate decoupling capacitor was 3300 pF.

VCM8: MB I w. suggested modifications

VCM8 is a trace from the same Isabel MB, after modification, taken when OFW was running. The modifications were the suggested ones. The value of the low MOSFET gate decoupling capacitor was 3300 pF.

Tests missing one modification

VCM9: MB I w. suggested modifications wo. ferrite

VCM9 is a trace from the same Isabel MB, after modification, taken during startup of VCORE. The modifications were the suggested ones, except the Vin ferrite wasn't present. The value of the low MOSFET gate decoupling capacitor was 3300 pF.

VCM10: MB I w. suggested modifications wo. ferrite

VCM10 is a trace from the same Isabel MB, after modification, taken during when OFW was running. The modifications were the suggested ones, except the Vin ferrite wasn't present. The value of the low MOSFET gate decoupling capacitor was 3300 pF.

VCM5: MB I w. suggested modifications wo. BST resistor

VCM5 is a trace from the same Isabel MB, after modification, taken during startup of VCORE. The modifications were the suggested ones except for no resistor in the BST circuit. The value of the low MOSFET gate decoupling capacitor was 3300 pF.

VCM6: MB I w. suggested modifications wo. BST resistor

VCM6 is the same as VCM5, with the trace taken while OFW was running.

Wrong Direction

VCM1: MB I w. ferrite and extra input cap

VCM1 is the Isabel MB after adding a ferrite (PL1 part) to path from Vin to PQ11/PC33/PC35 and an extra 10 uF input cap. No other modifications were used, and the results of this brute force approach were worse than no modifications! This trace was taken during startup of VCORE. VCORE shown at 500mV/div.

VCM2: MB I w. ferrite and extra input cap

VCM2 was the same as VCM1, taken while OFW was running (light load).

Right Direction

VCORE4: MB G w. basic improvements except series R in DH

VCORE4 is a trace from the Graham MB, modified with the suggested modifications, except no ferrite on Vin and no series resistor in DH. The lower MOSFET gate bypass cap was 3900 pF. The trace was taken while VCORE was starting up (heavy VCORE load). VCORE shown at 500mV/div.

VCORE5: MB G w. basic improvements except series R in DH

VCORE5 is a trace from the Graham MB, modified with the suggested modifications, except no ferrite on Vin and no series resistor in DH. The lower MOSFET gate bypass cap was 3900 pF. The trace was taken while OFW was running (light VCORE load).

Is the extra input bypassing crucial ?

VCORE2: MB G w. basic improvements except extra input cap

VCORE3: MB G w. basic improvements except extra input cap

VCORE2 and VCORE3 are traces from the Graham MB, modified with the suggested modifications, with the exception of not having a Vin ferrite, third input bypass cap, or series resistor in DH. The lower MOSFET gate bypass cap was 3900 pF. There were recorded during the startup of VCORE, which is a worst case for current draw from Vin. Watch how intermittent the startup is (Vin droop detected ?) Note the 0.5V influence on the (filtered) +1.8V supply.VCORE in VCORE3 shown at 500mV/div.

VCORE1: MB G w. basic improvements except extra input cap

VCORE1 is the same MB and modifications as VCORE2. The trace was taken while OFW was running (light VCORE load).

Is the lower MOSFET gate bypassing crucial ?

VCORE7: MB G w. basic improvements except gate bypass

VCORE7 is a trace from the Graham MB, modified with the suggested modifications, with the exception of not having a lower MOSFET gate bypass capacitor, a ferrite, or a series resistor in the DH line. The trace was taken during startup of VCORE. VCORE shown at 500mV/div.

VCORE6: MB G w. basic improvements except gate bypass

VCORE6 is a trace from the Graham MB, modified with the suggested modifications, with the exception of not having a lower MOSFET gate bypass capacitor, a ferrite, or a series resistor in the DH line. The trace was taken while OFW was running (light VCORE load).

Does slowing down DL help at all ?

The 1907DL signal shown significant over and undershoot. Does adding a series terminating resistor to it help prevent accidental turn-on ? No:

VCM11: MB I w. suggested modifications plus series resistor in DL

VCM11 is a trace from the same Isabel MB, after modification, taken during startup of VCORE. The modifications were the suggested ones. plus a series resistor in the DL line. The value of the low MOSFET gate decoupling capacitor was 3300 pF. The series resistor in 1907DL was 3.3 ohm.