The circuit in C1 showed problems at boot time. These measurements, taken on a reboot, show the SD power in green, +10V_GATE in yellow, +1.8V in blue, and +1.8V_GPIO in magenta. The problem is the bump where +3.3V starts to pull up the +1.8V rail!
The following measurement shows the SD power in green, +10V_GATE in yellow, Q35 (+3.3V) gate in blue, and Q50/Q28 gate (+1.8V) in magenta. It shows that we are lucky that SD_PWROFF is asserted early in boot. It is pulled up when +1.8V_GPIO is powered, but has a built-in delay (currently 6 mS) which kicks in just as the +3.3V switch starts to turn on.
The following measurement shows the SD power in green, +10V_GATE in yellow, SD_PWROFF in blue, and SD_1.8VSEL in magenta. While SD_PWROFF is pulled up immediately when +1.8V_GPIO is powered, SD_1.8VSEL doesn't reach a valid logic level until later.
The following measurement were all taken on a modified C1 motherboard. The circuit is shown below:
All measurements show the SD power in green, +1.8V in yellow, Q35 (+3.3V) gate in magenta, and Q50/Q28 gate (+1.8V) in blue. First, the improved boot timing:
Note that now the +1.8V switch gate voltage isn't powered if the +3.3V gate voltage is present, preventing the rail-rail short.
What happens when changing voltages ? Just changing the voltage selection GPIO doesn't result in a monotonic transition, due to a dead period guaranteeing no rail-rail shorts:
|+1.8V to +3.3V transition|
|+3.3V to +1.8V transition|
But powering off for a short period when changing the voltage, as specified in the SD specification, works fine. These are with a 10 mS delay between power-off and power-on:
|+3.3V power off, 10 mS delay, then a +1.8V power on|
|+1.8V power off, 10 mS delay, then a +3.3V power on|
The minimum amount of time to leave the switch off is determined by the control circuit time constants. The following show the performance of the switch with two delays between turn-off and turn-on (at the same voltage).
|+1.8V, 4 mS delay, note the incomplete power-off|
|+1.8V, 10 mS delay|
|+3.3V, 4 mS delay, note the incomplete power-off|
|+3.3V, 10 mS delay|
A version which only fixes the startup problem without changing the switching topology is provided below. The problems with this design are two: an intermediate level of SD_1.8VSEL may cause a +1.8V to +3.3V short, and it requires that +3.3V_NAND be routed to the SD switch.