set value *(unsigned long *)0xD0000100 = 0x000E0001 !#____MMAP0 set value *(unsigned long *)0xD0000110 = 0x400E0000 !#____MMAP1 set value *(unsigned long *)0xD0000020 = 0x00222430 !#____SDRAM_CONFIG_TYPE1_CS0 set value *(unsigned long *)0xD0000030 = 0x00222430 !#____SDRAM_CONFIG_TYPE1_CS1 set value *(unsigned long *)0xD0000B40 = 0x00000000 !#____SDRAM_CONFIG_TYPE2_CS0 set value *(unsigned long *)0xD0000B50 = 0x00000000 !#____SDRAM_CONFIG_TYPE2_CS1 set value *(unsigned long *)0xD0000050 = 0x911500CA !#____SDRAM_TIMING1 set value *(unsigned long *)0xD0000060 = 0x646602C4 !#____SDRAM_TIMING2 set value *(unsigned long *)0xD0000190 = 0xC2003053 !#____SDRAM_TIMING3 set value *(unsigned long *)0xD00001C0 = 0x44F2A186 !#____SDRAM_TIMING4 set value *(unsigned long *)0xD0000650 = 0x000F00F1 !#____SDRAM_TIMING5 set value *(unsigned long *)0xD0000660 = 0x04040200 !#____SDRAM_TIMING6 set value *(unsigned long *)0xD0000080 = 0x90045000 !#____SDRAM_CTRL1 set value *(unsigned long *)0xD0000090 = 0x00100010 !#____SDRAM_CTRL2 set value *(unsigned long *)0xD00000F0 = 0xC0000000 !#____SDRAM_CTRL3 set value *(unsigned long *)0xD00001A0 = 0x20C0C409 !#____SDRAM_CTRL4 set value *(unsigned long *)0xD0000280 = 0x01010101 !#____SDRAM_CTRL5_ARB_WEIGHTS set value *(unsigned long *)0xD0000760 = 0x00000001 !#____SDRAM_CTRL6_ODT_CTRL set value *(unsigned long *)0xD0000770 = 0x01000002 !#____SDRAM_CTRL7_ODT_CTRL2 set value *(unsigned long *)0xD0000780 = 0x00000133 !#____SDRAM_CTRL8_ODT_CTRL2 set value *(unsigned long *)0xD00007B0 = 0x01010101 !#____SDRAM_CTRL11_ARB_WEIGHTS_FAST_Q set value *(unsigned long *)0xD00007D0 = 0x00000001 !#____SDRAM_CTRL13 set value *(unsigned long *)0xD00007E0 = 0x00000000 !#____SDRAM_CTRL14 set value *(unsigned long *)0xD0000540 = 0x00000000 !#____MCB_CTRL4 set value *(unsigned long *)0xD0000570 = 0x00000001 !#____MCB_SLFST_SEL set value *(unsigned long *)0xD0000580 = 0x00000000 !#____MCB_SLFST_CTRL0 set value *(unsigned long *)0xD0000590 = 0x00000000 !#____MCB_SLFST_CTRL1 set value *(unsigned long *)0xD00005A0 = 0x00000000 !#____MCB_SLFST_CTRL2 set value *(unsigned long *)0xD00005B0 = 0x00000000 !#____MCB_SLFST_CTRL3 set value *(unsigned long *)0xD0000180 = 0x00000000 !#____CM_WRITE_PROTECTION set value *(unsigned long *)0xD0000210 = 0x00000000 !#____PHY_CTRL11 set value *(unsigned long *)0xD0000240 = 0x80000000 !#____PHY_CTRL14 set value *(unsigned long *)0xD0000240 = 0xA0000000 !#____PHY_CTRL14 set value *(unsigned long *)0xD0000240 = 0x80000000 !#____PHY_CTRL14 set value *(unsigned long *)0xD0000200 = 0x0011311C !#____PHY_CTRL10 print "**** Result of Pad drive strength auto cal (ZPR in [23:20], ZNR in [19:16] of PHY_CTRL14)\n\n" show mem /length=4 /size=long 0xD0000240 print " __^^____\n" set value *(unsigned long *)0xD0000200 = 0x0010311C !#____PHY_CTRL10 set value *(unsigned long *)0xD0000140 = 0x20004044 !#____PHY_CTRL3 set value *(unsigned long *)0xD00001D0 = 0x1FF84849 !#____PHY_CTRL7 set value *(unsigned long *)0xD00001E0 = 0x0FF00840 !#____PHY_CTRL8 set value *(unsigned long *)0xD00001F0 = 0x00000084 !#____PHY_CTRL9 set value *(unsigned long *)0xD0000230 = 0x20100088 !#____PHY_CTRL13 set value *(unsigned long *)0xD0000E10 = 0x00100080 !#____PHY_DLL_CTRL1 set value *(unsigned long *)0xD0000E20 = 0x00100080 !#____PHY_DLL_CTRL2 set value *(unsigned long *)0xD0000E30 = 0x00100080 !#____PHY_DLL_CTRL3 set value *(unsigned long *)0xD0000E40 = 0x00000000 !#____PHY_CTRL_WL_SELECT set value *(unsigned long *)0xD0000E50 = 0x00000000 !#____PHY_CTRL_WL_CTRL0 set value *(unsigned long *)0xD0000120 = 0x01000001 !#____USER_INITIATED_COMMAND0 print "**** DDR Init completed bit0=1 of DRAM_STATUS:\n" show mem /length=4 /size=long 0xD00001B0 print " _______^\n" print "\n" set value *(unsigned long *)0xD0000120 = 0x01001000 !#____USER_INITIATED_COMMAND0 print "**** DDRPHY: DLL_DELAY_OUT delay value in bits 15:8 of register PHY_CTRL14:\n" show mem /length=4 /size=long 0xD0000240 print " ____^^__\n" print "\n"